System Verilog Design Engineer

Petah Tikva, Israel
Full time

The position

At Mobileye, we foster a hybrid-friendly environment, combining work from office and home.

Our vision is to enable the autonomous vehicle dream with best in class, cutting-edge, imaging radar. We are looking for a system Verilog design engineer to join the development of the next generation of RF silicons that are part of our Software Defined Radar. The group hosts a diverse team of scientists, engineers and developers to research, realize and bring to market innovative new silicons. You will be part of a winning RF design team in a fast-paced startup-like environment, working on many different RF and analog components of the RF silicons in the most advanced nano-scale Technologies.

What will your job look like?

  • Develops and supports Behavioral Models (BM) design for Analog/RF circuits.
  • Develop custom Analog/RF Behavioral Models design and simulation using advanced tools, doing integration for entire chip level while performing fullchip verification
  • In charge of Full chip Netlisting and delivery to Back End after full verification of connectivity.

All you need is:

  • BSc degree in Electrical Engineering
  • Knowledge of Basic RF/Analog/Mixed signal circuits
  • 3-5 years of experience in VHDL / System Verilog / Verilog
  • Experience in cadence tools – an advantage
  • Knowledge in Linux environment - an advantage
  • Motivated and eager to learn, independent and OOB thinking
  • Fast learner, Organized and methodic
  • Excellent interpersonal and communication skills
Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!